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 LVS / PDK/ Runsets libraries development
Physical design and synthesis
Static timing analysis
Place and route.
Development of clocking and reset architectures,
Development of timing constraints,
Logic Synthesis,
Static timing,
DFT,
Place & Route,
CTS,
Timing closure of Design,
Logic Equivalence Checking.
Managing external backend services
** Assura, Calibre, IC design Tools, Virtuoso. |
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