Rachip verification team integrates as part of Mellanox's team in the development of the various products.
Mellanox Technologies is a leading supplier of end-to-end InfiniBand and Ethernet interconnect solutions and services for servers and storage. Mellanox offers a choice of fast interconnect products: adapters, switches, software and silicon that accelerate application runtime and maximize business results for a wide range of markets including high performance computing, enterprise data centers, Web 2.0, cloud, storage and financial services.
Rachip team is part of the Chip Design verification team that develops verification environments using Specman, and NC-Sim, while facing with InfiniBand, PCIe, and Ethernet protocols. Rachip team also deals with SW verification - coding tests in python in purpose to check product that uses IPoIB protocol.
Rachip verification team integrats as part of Zoran's team in the various blocks of the COACH (Camera on a Chip). Zoran's chips are about 70% of the digital cameras in the world. The work includes development of verification environments in e, specman, eRM methodology using ncsim & vmanager. These environments are block level. The Rachip's team deals with the SOC ( System on a Chip ) envs too, faces with ABUS, CBUS, PBUS protocols while testing ARCs' functionality and communication with CPU. These tests written in "C" & Assembler.
Rachip verification team is acting together with the Microsemi verification team, developing varied verification environments, facing with mixed signal integrated environment. Some of the Microsemi's chips are working with high-voltage Power over Ethernet (PoE) applications, (the PoE technology describes a system to pass electrical power safely, along with data, on Ethernet cabling, According to the IEEE standard for PoE requirements) in parallel with some ports. Another project is a verification environment for LED backlight system. The environments are in system level architecture, written in system Verilog language. Rachip team also supports in the efforts to upgrade existing environments to advanced methodology and in the automation process by developing very complex and useful scripts.
Rachip upgrades a verification environment of Rad's bridge that maximize Ethernet throughput for small and medium-size businesses. The new environment is written in e, specman according to eRM methodology, and allows future reuse. The work includes writing the new environment (adding new features), debug and running regressions using ncsim simulator.
Rachip PDK team is acting together with the Tower PDK team, Rachip team is Working especially for Design Rule Check(DRC), which is the area of Electronic Design Automation. It determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules. Design rule checking is a major step during Physical verification signoff on the design. DRC is a very computationally intense task. Usually DRC checks will be run on each sub-section of the ASIC to minimize the number of errors that are detected at the top level.DRC written in Calibre and Assura language.
An Israeli start-up developing a very complex and challenging TDM networking ASIC, Rachip provides a verification consulting, plays a main role in the developing activity of SONET-SDH eVCs, fully eRM compliance, using IES and eManager tools.
Rachip supplies outsourcing and management services for developing Verification environments (eVCs) for a complex Network processing FPGA, Rachip developing team acting together with the verification team of NSN to verify Ethernet, Fap, QDR and Hab features using Specman and NCSim, in addition Rachip creates a detailed vPlan including the whole FPGA coverage items.
Rachip supplies on-site verification services for verifying the Cadence tools using e, System Verilog and Verilog languages, Rachip supplies off-site services for developing the PCIExpress UVC, our developers participate in the UVC features development, match the product for Cadence customers' environment, increase the CMS package and OVM tests using eManager and System Verilog.
Rachip supplies outsourcing and management services for developing verification environment for Tessera's digital camera focus IP. Rachip team upgrades the existing verification environment from Verilog to System Verilog, inserts System Verilog assertions (SVA) and develops SV coverage environment.