Project Info

Electronic System Level is now an established
approach at most of the world’s leading System-on-a-
chip (SoC) design companies, and is being used
increasingly in system design.

Rachip Team Part
Client
Technologies Involved
Rachip Team Part
  • Transaction-Level Modeling is key to exploiting ESL languages and design methodologies.
  • Electronic System-Level languages enable the use of higher levels of abstraction in hardware modeling.
  • Improved hardware design productivity
  • HW/SW co-design
  • Transformation and refinement of models through synthesis is merging.
  • Developing operational ESL models of systems remains a very challenging task.
  • ESL design methodologies must address the entire design flow, not just the hardware.

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קיצור תולדות הזמן בעידן המודולינג

Client

ESL design and verification is an electronic design methodology that focuses primarily on the higher abstraction level concerns.

  • Model the behavior of the entire system using SystemC language.
  • Integrate with other players in the development progress, like Firmware, Driver, Ucode, etc.
  • Connect to test environment for simulate the model behavior – easy way for find HW bugs before the RTL implementation.

Technologies Involved
  • A set C++ class library to add hardware modeling constructs
  • Simulation kernel
  • Supports different levels of abstraction
  • Untimed Functional Model
  • Transaction Level Model
  • Bus Function Model