Rachip verification team integrates as part of PLSense team in the development of the various products.
Rachip Team Part
Rachip verification engineers took responsibility for the verification of the AON chip. The chip includes SMM, PMU and CLKGEN blocks – those blocks were checked in block level and in full chip. Much effort was invested to overcome Timing synchronization challenges. The tasks were completed successfully before the deadline. Rachip also took responsibility for Embedded SW. The job included writing API and drivers for PLSense MCU chip. The verification environments were written in System Verilog language and C++ language.
PLSense offers a unique and revolutionary generic approach that goes far beyond existing conventions on the market. In fact, PLSense provides a complete solution for IoT SoC design that only demands minimum energy operation for the targeted performance in a wide range of frequencies (up to 100MHz) dynamically required by the application. While extending the system battery life by a factor of 5-10X from existing solution today.
PLSense provides a unique, revolutionary and complete generic approach for IoT SoC design that achieves minimum energy operation for the targeted performance in a wide range of frequencies (up to 100MHz) dynamically required by the application. While achieving up to 90% energy reduction, as compared to the most advanced competitors, PLSense designs are more reliable, provide better yield and have a longer lifetime