QLogic

Rachip verification engineers took part in the efforts of verifying a few blocks of the a version of Intelligent Ethernet Adapter Chip. The verification was based on the Specman Elite verification system. Rachip was responsible for the verification of the management of the chip’s power-up sequencing, and of Ethernet blocks which control the Tx and Rx DataPath transfers. The work included writing sequences, debug the environment and the design and implementation of the full functional coverage plan. The verification process required out of the box innovative thinking for overcoming challenges encountered during the work. The team cooperated with other verification groups around the world.