Rachip team integrates as part of Tower Layout team in the development of the various products.
Rachip Team Part
Rachip engineers are the owners of Design Rule Checking, the work includes: use the PDK to design, simulate, draw and verify the design before handing the design back to the foundry to produce chips. The rules are written in the languages: Assura by Cadence Design Systems and Calibre by Mentor Graphics, using the tools: CALIBRE DESIGN REV and VIRTUOSO.
TowerJazz has worked with EDA partners to create design flows for our analog/mixedsignal 180nm power management process. This collaboration provides mutual customers with a complete design and manufacturing solution and the fastest path to silicon realization. TowerJazz’s AMS Reference Flow 1.0 includes a comprehensive design flow using a Band Gap Reference circuit that demonstrates a practical and efficient design methodology. The combination of TowerJazz’s advanced power management process with detailed design and layout tools from EDA vendors allow IC designers the ability to quickly and accurately create power management chips, including driver ICs, battery and portable power management, and power control for PCs for consumer, communications, and computing applications.
Complete documentation covering the overall flow as well as the detailed reference flow steps is also included. Mutual customers can quickly utilize the complete power management design flow from schematic capture to simulation, layout, physical verification, and parasitic extraction. The comprehensive reference flow also includes valuable productivity features to help designers achieve an on-time and onbudget tape-out.
TowerJazz offers a broad range of customizable process technologies, including SiGe BiCMOS and RF CMOS (SOI and bulk) for radio frequency and high performance analog (HPA) applications; CMOS image sensor (CIS); power management, including BCD and 700V, and its patented Y-Flash, the leading solution for non-volatile memory (NVM); CMOS; mixed-signal CMOS; and MEMS capabilities.