Chip Verification, Validation and Other Design Cycle Terms Explained
When designing an ASIC chip, you will go through a set life cycle.
This includes setting out the specs, deciding upon the architecture, completing verification
and then after a tapeout, completing testing and validation.
The terms ‘verification’, ‘validation’ and ‘testing’ sound very similar, but each are distinct parts of
designing a custom chip like an ASIC, ASSP or other SoCs.
Tapeout is the result of the long SoC design process when the circuit photomask graphic is sent to be physically created.
SoC Verification involves testing a design against a design spec.
This happens after the planning stage of a project, throughout the building stage until tapeout.
Verification is all about making sure the chip you’re building is functional, attempting to reduce all errors
that would come from not adhering strictly to the design brief.
It can even start when specifications are being formed, and when architecture and microarchitecture are being developed.
As the chip gets more complex, more targets need to be verified, including performance targets, power targets and security essentials of design.
RTL is how most chip verification happens, involving simulating a design model to test it is up to scratch.
If it passes RTL, other simulations like power-aware simulations, static checks, emulation prototyping and dynamic checks can be used to help verify the chip.
Verification checks for bugs in design before it gets expensive to fix after tapeout.
Validation occurs after tapeout. The physical chip is tested in a lab to make sure it is functioning as expected.
The chip is assembled into a test or reference board with other components, and every single way the end-user might use the final product is simulated and tested.
If these uses are validated, the design qualifies as usable for true deployment.
Validation is conducted by hardware and software engineers as the hardware’s performance in a digital environment needs to be assessed.
Before a chip is packaged, it needs to be tested.
Although verification and validation both involve tests, chip testing is different:
it involves screening chips as a form of quality control.
It involves testing for defects (ones that happen related to a function or random flaws), reliability and its electrical characterization.
There are several different essential tests:
- Wafer Sort Tests – a test that characterizes the critical parameters of the transistors and general technology before the dies are packaged to identify dud dies.
- Burn-In Stress tests – chips need to operate well at high temperatures, so they are tested when they are packaged to see how reliable they are at high temperatures.
- IC tests – equipment like ATE take individual chips and test response checks and pattern stimulus automatically
- Electrical Characterization tests – these tests involve testing voltage, as well as what their shmoo plot looks like.
Verification, validation, and testing are all essential steps along an SoC design cycle, and without them, the world of computing would be rife with mistakes.
Performing verification properly is highly essential to a cost-effective design life cycle.