Experienced Physical Design (Backend) engineer

Take ownership and responsibility on closure of digital oriented Top Level Partition / Block at VLSI 28nm or 16nm geometry project. Backend flow based on Cadence toolset with emphasis on Place & Route techniques and Timing Closure.
Perform with excellence and synergy while reporting to the Project Leader
Requirements:
• Serviceability orientation and beneficial interpersonal relationship personality – is a must
• Relevant experience with closure of full chip RTL2GDS or NL2GDS – is highly desired and big plus
• Relevant experience with STA closure of 2-3 Partitions [top level blocks] – is a must
• Relevant experience with P&R at 28nm or alike advanced geometries – is a must
• Relevant experience with coloring P&R at 16nm or alike advanced geometries – is a plus
• Experience with coping techniques of challenging floorplan – is a plus
• Experience with STA closure of Partitions [top level blocks] with Memories and / or CPU core – is a plus
• Relevant experience with Cadence tools flow – is highly desired
• Experience with providing VLSI / ASIC services – is a plus



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