We’re looking for Junior Verification Engineer to join our company

Requirements:

• 2-3 years of experience in HW Verification developing, methodologies and implementation.
• Experience in System Verilog, UVM
• Good programming skills in Verilog, VHDL, C, Assembly, Perl
• B.Sc in Electrical Engineering graduating with honors

לשליחת קורות חיים

צרף/פי קובץ



מספר משרה

Leave a Reply

Your email address will not be published. Required fields are marked *