Rachip Backend team carries out SoC from RTL → GDS. Our team is a professional services group delivering value-added ASIC implementation solutions to our customers, resulting in first-pass silicon success. We add value by remaining on the cutting edge of EDA tools & Methodologies, So that we can meet the challenge of continued growth in design complexity and shrinking geometries.
We have extensive experience in implementing of complex designs with clock frequency over 2Ghz. Our customers include global silicon companies with the most advanced CMOS processes. The group consists of 20 Backend engineers and 4 team leaders.
Rachip provides services in the following areas:
- Clock and reset architectures.
- Design for test- Memory, Analog IP, High Speed I/O, Serdes.
- RTL-to-gate level netlist Synthesis.
- Hierarchical timing budgeting and floor plan design.
- Hierarchical Power budgeting and Power grid design.
- Qualifying libraries, existing netlist Vs RTL and design constraints.
- Timing and SI-aware place and rout .
- Full-chip RC extraction.
- Full-chip timing/SI closure, static timing analysis and sign-off.
- Full-chip physical verification.(DRC)
- Full chip Logic Vs Schematic verification.(LVS)
- Chip finishing to Tape-Out
- Automatic Test Pattern Generation. (ATPG)
- Spice simulation and analysis.