Self Project for Training

Based on “open source projects community” from the European Space Agency LEON processor
An Overview
Rachip is an R&D Center, SW & HW development services. Each year we train engineers in the arena of chip development, including Chip Design, Verification and Backend. As part of our intensive training, we decided to set up a self-training project. This program benefits both, our working staff and productivity in the “open source projects community”. We started with a simple sub-system, based on verified design code from the European Space Agency LEON processor. We aimed to acquire knowledge in UVM verification for System On Chip (SOC), such as ARM processors sub-system, including AHB and APB.
In our DUT code, there are two DMA channels, driving data to two AHB masters. These two AHB masters are connected to an Arbiter. The arbiter has single output, which is connected to an AHB to APB module. At the end of this module is a memory device, with an APB interface.
All DUT modules are written in VHDL in “LEON style”, except the Arbiter. We added a few features to the Arbiter (DUT) using a simple style.
All the LEON VHDL is wrapped with a system Verilog bench. The bench allows access for our UVM verification. The first release of this verification environment is passive. It supports only monitors and scoreboard for checking data integrity.
The following block diagram shows assorted modules of the DUT and UVM verification environment.

Some notes about the verification environment:
• System Verilog UVM based environment.
• In the first release, only the passive part is implemented: i.e. AHB monitors, scoreboard and coverage.
• Only AHB bus monitors are required for the first release.
• First release monitors are AHB bus of master 0 and 1 (scoreboard inputs). The output is taken from the AHB bus in the input of slave 0.
• The second release generates data in DMA channels and enables back to back transaction on the AHB bus. Coverage is also included in the second release.
• The third release uses UVM end of test mechanism.
• The fourth release includes an APB monitor at the primary output of the DUT.

Rachip is an engineering company that provides SW & HW development services. The company has vast experience in Embedded Real Time systems, FPGA/ASIC development, QA and Automation as well as Web/Mobile apps. Rachip acts as a one-stop-shop for industries such as Semiconductors, Medical, Fintech, Automotive, Communication Systems, IoT and more. It works closely with multinational companies as well as startups, providing its varied customers with highly skilled local labor, Enabling them with project scope & budget flexibility.
You are welcome to contact us for further information: www.rachip.com.

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