Leading verification tasks.
Creating and implementing test plans for module and system level of RTL design.
Implementing SystemVerilog/UVM based verification components.
Integrating verification IPs.
Work in a matrix organization with all disciplines – Design, System, SW, System Validation
B.Sc. in electrical engineering or computer science.
At least 4 years of experience in UVM methodology (System Verilog)
High level of English.
Experience with both Verilog & VHDL
Experience with Xilinx/Synopsys tools.
Experience with svn.
Experience with scripting language – Python, Perl, Bash.
Experience with ARM architecture and bus protocols.
Experience with Matlab & Simulink.
Knowledge in analog & digital networks